Устройства вроде DRACO показали ральность построения больших функциональных асинхронных систем. Как и любой прототип ИС имеет свои проблемы. Известно о 2 дефектах в асинхронной части системы: проблема с мощностью задатчиков в умножителе (которая не была выявлена при моделировании) и логическая ошибка в модуле предвыборки , которая ошибочно показывает 'последовательный' цикл при некоторых условиях (при выполнении кода из внешней DRAM). Ни один из них не связан с асинхронной природой устройства и оба без труда исправляются. Процессор сравним с ARM9 произведенного то тем же технологическим нормам по размеру, производительности и потребляемой мощности; предварительные исследования показали значительно меньшее ЭМИ.
В данной главе представлены возможные решения (хотя они и не единственные!) многих проблем возникающими перед разработчиком сложных асинхронных систем обработки и зранения данных. Большинство проектов описанных в начале главы созданы академическими группами и классифицируются как «исследовательские»; однако, сложность современных сситем на кристалле превышает возможности даже больших академических групп. Эти проеты показывают, что крупные функциональные асинхронные проекты не только возможны, но могут быть конкурентными и обладают некоторыми уникальными свойствами вроде управления питанием и ЭМИ. Асинхронные соединения могут быть едиснтвеным решением для юольших устройств с локальными синхросигналами. Проекты асинхронных ИС уже готовы к «развертыванию».
Asynchronous technology has existed since the first days of digital electronics - many of the earliest computers did not employ a central clock signal. However, with the development of integrated circuits the need for a straightforward design discipline that could scale up rapidly with the available transistor resource was pressing, and clocked design became the dominant approach. Today, most practising digital designers know very little about asynchronous techniques, and what they do know tends to discourage them from venturing into the territory. But clocked design is beginning to show signs of stress - its ability to scale is warning, and it brings with it growing problems of excessive power dissipation and electromagnetic interference.
During the reign of the clock, a few designers have remained convinced that asynchronous techniques have merit, and new techniques have been developed that are far better suited to the VLSI era than were the approaches employed on early machines. In this book we have tried to illuminate these new techniques in a way that is accessible to any practising digital circuit designer, whether or not they have had prior exposure to asynchronous circuits.
In this account of asynchronous design techniques we have had to be selective in order not to obscure the principal goal with arcane detail. Much work of considerable quality and merit has been omitted, and the reader whose interest has been ignited by this book will find that there is a great deal of published material available that exposes aspects of asynchronous design that have not been touched upon here.
Although there are commercial examples of VLSI devices based on asynchronous techniques (a couple of which have been described in this book), these are exceptions - most asynchronous development is still taking place in research laboratories. If this is to change in the future, where will this change first manifest itself?
The impending demise of clocked design has been forecast for many years and still has not happened. If it does happen, it will be for some compelling reason, since designers will not lightly cast aside their years of experience in one design style in favour of another style that is less proven and less well supported by automated tools.
There are many possible reasons for considering asynchronous design, but no single 'killer application' that makes its use obligatory. Several of the arguments for adopting asynchronous techniques mentioned at the start of this book - low power, low electromagnetic interference, modularity, etc. - are applicable in their own niches, but only the modularity argument has the potential to gain universal adoption Here a promising approach that will support heterogeneous timing environments is GALS (Globally Asynhronous Locally Synchronous) system design. An asynchronous on-chip interconnect - a 'chip area network' such as Chain (described on page 312) - is used to connect clocked modules. The modules themselves cixn be kept small enough for clock skew to be well-contained so that straightforward synchronous design techniques work well, and different modules can employ different clocks or the same clock with different phases. Once this framework is in place, it is then clearly straightforward to make individual modules asynchronous on a case-by-case basis,
Here, perhaps unsurprisingly, we see the need to merge asynchronous technology with established synchronous design techniques, so most of the functional design can be performed using well-understood tools and approaches. This evolutionary approach contrasts with the revolutionary attacks described in Part III of this book, and represents the most likely scenario for the widespread adoption of the techniques described in this book in the medium-term future.
In the shorter term, however, the application niches that can benefit from asynchronous technology are important and viable. It is our hope in writing this book that more designers will come to understand the principles of asynchronous design and its potential to offer new solutions to old and new problems. Clocks are useful but they can become straitjackets. Don't be afraid to think outside the box!
For further information on asynchronous design see the bibliography at the end of this book, the Asynchronous Bibliography on the Internet , and the general information on asynchronous design available at the Asynchronous Logic Homepage, also on the Internet .
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